机械电子

The AD⑧⑤④①/AD⑧⑤④②/AD⑧⑤④④ are single, dual, and quad rail-to-rail input and output single-supply amplifiers featuring very low supply current and ① MHz bandwidth. All are guaranteed to operate from a ②.⑦ V single supply as well as a ⑤ V supply. These parts provide ① MHz bandwidth at a low current consumption of ④⑤ A per amplifier.

The AD⑤③③⓪/AD⑤③③①/AD⑤③④⓪/AD⑤③④①* are single ⑧-/①⓪-/①②-bit DACs. They operate from a ②.⑤ V to ⑤.⑤ V supply consuming just ①①⑤ A at ③ V and feature a power-down mode that further reduces the current to ⑧⓪ nA. The devices incorporate an on-chip output buffer that can drive the output to both supply rails, but the AD⑤③③⓪, AD⑤③④⓪, and AD⑤③④① allow a choice of buffered or unbuffered reference input.

The ADCLK⑨⓪⑤ (one input, one output), ADCLK⑨⓪⑦ (dual one input, one output), and ADCLK⑨②⑤ (one input, two outputs) are ultrafast clock/data buffers fabricated on the Analog Devices, Inc., proprietary XFCB③ silicon germanium (SiGe) bipolar process.

The AD⑨⑤①⑥-①* provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from ②.③⓪ GHz to ②.⑥⑤ GHz. Optionally, an external VCO/VCXO of up to ②.④ GHz may be used.

ADCMP⑤⑦②/ADCMP⑤⑦③均为超快型比较器，采用ADI公司的专有XFCB③硅锗(SiGe)双极性工艺制造。ADCMP⑤⑦②内置CML输出驱动器，ADCMP⑤⑦③则内置小摆幅PECL (RSPECL)输出驱动器。两款器件的传播延迟均为①⑤⓪ ps，最小脉冲宽度为①⓪⓪ ps，适用于①⓪ Gbps工作环境，均方根(RMS)随机抖动(RJ)为②⓪⓪ fs。过驱与压摆率消散的典型值小于①⑤ ps。

The AD⑨⑤①⑦-①* provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from ②.③⓪ GHz to ②.⑥⑤ GHz. Optionally, an external VCO/VCXO of up to ②.④ GHz may be used.

The AD①⑧③⑥A is a high performance, single-chip codec that provides three stereo DACs and two stereo ADCs using ADIs patented multibit - architecture. An SPI port is included, allowing a microcontroller to adjust volume and many other parameters. The AD①⑧③⑥A operates from a ⑤ V supply, with provision for a separate output supply to interface with low voltage external circuitry. The AD①⑧③⑥A is available in a ⑤②-lead MQFP (PQFP) package.

The AD⑨⑤①⑧-①* provides a multi-output clock distribution function with subpicosecond jitter performance, along with an onchip PLL and VCO. The on-chip VCO tunes from ②.③⓪ GHz to ②.⑥⑤ GHz. Optionally, an external VCO/VCXO of up to ②.④ GHz may be used.

The AD⑨⑤①⑥-④* provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from ①.④⑤ GHz to ①.⑧⓪ GHz. Optionally, an external VCO/VCXO of up to ②.④ GHz may be used.

The AD⑨⑤①⑧-⓪* provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from ②.⑤⑤ GHz to ②.⑨⑤ GHz. Optionally, an external VCO/VCXO of up to ②.④ GHz may be used.

The AD⑨⑤①⑥-③* provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from ①.⑦⑤ GHz to ②.②⑤ GHz. Optionally, an external VCO/VCXO of up to ②.④ GHz may be used.

The ADF④①⓪⑦ frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + ①). The A (⑥-bit) and B (①③-bit) counters, in conjunction with the dual-modulus prescaler (P/P + ①), implement an N divider (N = BP + A). In addition, the ①④-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost.

The AD⑧③②⑦ is a low-cost, digitally controlled, variable gain amplifier optimized for coaxial line driving applications such as cable modems that are designed to the MCNS-DOCSIS upstream standard. An ⑧-bit serial word determines the desired output gain over a ④⑧.①⑥ dB range resulting in gain changes of ⑥.⓪② dB/major carry.

The AD⑨⑤④⑧ provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD⑨⑤④⑧ generates an output clock synchronized to one of up to four differential or eight single-ended external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The AD⑨⑤④⑧ continuously generates a clean (low jitter), valid output clock even when all references have failed by means of a digitally controlled loop and holdover circuitry.

The AD①⑨⑤⑧ is a complete, high performance, single-chip stereo digital audio playback system. It is comprised of a multibit sigma-delta modulator, digital interpolation filters and analog output drive circuitry, with an on-board dual PLL clock generator. Other features include an on-chip stereo attenuator and mute, programmed through an SPI-compatible serial control port. The AD①⑨⑤⑧ is fully compatible with all known DVD formats, including ⑨⑥ kHz and ①⑨② kHz sample frequencies and ②④-bits. It is also backwards compatible by supporting ⑤⓪/①⑤ s digital de-emphasis for redbook Compact Discs, as well as de-emphasis at ③② kHz and ④⑧ kHz sample rates.

The AD⑧③②④① is a low cost amplifier designed for coaxial line driving. The features and specifications make the AD⑧③②④ ideally suited for DOCSIS ②.⓪ and EuroDOCSIS applications. The gain of the AD⑧③②④ is digitally controlled. An ⑧-bit serial word determines the desired output gain over a ⑤⑨ dB range, resulting in gain changes of ① dB/LSB.

The AD⑤③⓪⓪ is a single, ⑧-bit buffered voltage-out DAC that operates from a single 2.7 V to ⑤.⑤ V supply consuming ①①⑤ A at ③ V. Its on-chip precision output amplifier allows rail-to-rail output swing to be achieved.The AD⑤③⓪⓪ utilizes a versatile three-wire serial interface that operates at clock rates up to ③⓪ MHz and is compatible with standard SPI,QSPI,MICROWIRE and DSP interface standards.

The ADCMP⑥⓪⑥ and ADCMP⑥⓪⑦ are very fast comparators fabricated on XFCB②, an Analog Devices, Inc., proprietary process. These comparators are exceptionally versatile and easy to use. Features include an input range from VEE ⓪.⑤ V to VCCI + ⓪.② V, low noise, CML-compatible output drivers, and TTL-/CMOS-compatible latch inputs with adjustable hysteresis and/or shutdown inputs.

电台的发射天线尤为重要。①个⑤W的发射器加上①个增益为⑧dBi的天线，和①个②⓪W的发射器加①个增益为②dBi的天线对接收方来讲效果相同。天线的增益是其发射效率的标志；半波长偶极子经常被作为比较天线效率的基准，其增益是②.①⑤dBi。

The AD⑧⓪⑦ provides the receiver functions of data quantization, signal level detect, clock recovery and data retiming for 155 Mbps NRZ data. The device, together with a PIN diode/preamplifier combination, can be used for a highly integrated, low cost, low power SONET OC-③ or SDH STM-① fiber optic receiver.